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2025-10-31
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This article introduces the core content of the ARM AXI bus protocol. It first reviews the development history of the AMBA bus and explains the importance of AXI as an on-chip synchronous parallel bus in SoC design. The AXI bus features high performance, low latency, and high frequency, and supports independent read/write channels, burst transfers, multiple outstanding transfers, out-of-order completion, and unaligned data transfers. The article elaborates on the AXI master-slave mechanism and the five independent transfer channels (read address, read data, write address, write data, write response), and explains the VALID/READY handshake signals and the difference between transfers and transactions. In addition, the article discusses the roles of parameters such as AxLEN, AxSIZE, and AxBURST in burst transfers, as well as the functions of access permissions (AxPROT), cache attributes (AxCACHE), response packets (RRESP/BRESP), write strobes (WSTRB), and QoS signals (AWQOS/ARQOS), and describes the dependencies between channels. Overall, this article provides a systematic technical overview for understanding the AXI bus protocol.
Reference documents:
Document: AMBA AXI and ACE Protocol Specification, issue H, part A & Part E
AMBA bus development history
Application of the AXI bus
AMBA bus development history
AXI basic concepts: channels, transfers, transactions
What is a bus
A bus consists of a single signal or a group of signals that transmit data or control information.
On the bus, the sender encodes and sends information according to the protocol-defined combination of high and low levels, and the receiver decodes it.
External bus and internal bus
- External buses connect peripheral devices and may suffer from external interference, connector and PCB losses, and poor signal integrity.
I2C，UART，SPI，PCIe，USB
- Internal buses are used inside SoCs. Since the routing is within the chip and distances are extremely short, many interference and signal integrity issues do not need to be considered.
AXI，UPI（intel）
Parallel bus and serial bus
- Parallel: multiple data bits are transmitted simultaneously. The need to coordinate data limits the frequency of parallel transmission and makes it prone to interference.
- Serial: only one link, but the frequency can be made very high to increase transmission speed.
Features of the AXI bus
- The AXI bus is an on-chip synchronous parallel bus.
- Advantages of the AXI bus
- High performance: high bandwidth, low latency, high frequency
- Flexible scalability of bus width and topology connections
- Compatible with AHB and APB buses
- Features of the AXI bus
- Independent address/control and data channels (separate read & write channel)
- Supports burst transfers
- Supports outstanding transfers (multiple outstanding addresses)
- No strict timing requirements between address and data phases (no strict timing between address and data phases)
- Supports out-of-order transfers (out-of-order transaction completion)
- Supports unaligned data transfer (support unaligned data transfer)
AXI topology
AXI uses a master-slave mechanism
- The master initiates requests
- The slave responds to requests
AXI channels
AXI defines 5 independent transfer channels (channel) to improve bandwidth
- Read address channel: AR
- Read data channel: R
- Write address channel: AW
- Write data channel: W
- Write response channel: B
Each channel is not a single signal line, but a group of signal lines
Write transaction
- The address channel contains transfer control information
- Transfer transaction steps:
- The master initiates a write transfer through the write address channel, including address and control information
- Master writes data to slave via the write data channel
- Slave responds via the write response channel
Read transaction
- Master sends address and control information to slave via the read address channel
- Slave returns data via the read data channel, and the response information is included in the returned data
Handshake signals (Handshake process)
- All 5 channels use the same handshake signals: VALID/READY handshake process
- The source generates the VALID signal to indicate that address, data, control information, etc., are ready
- The destination generates the READY signal to indicate that it starts accepting information
The handshake occurs only when both READY and VALID signals are active
Difference between transfer and transaction
Transfer
A single handshake process transfers data once
transaction
There are multiple handshake processes, composed of multiple transfers
Taking write as an example, address and control information are transmitted through the write address channel. Then data is transferred through the write data channel. Finally, a response is made through the write response channel.
There are 3 transfers in total
Example: Write transaction: single data item
Example: Read transaction: single data item
Example: Read transaction: multiple data items
Channel signals and transaction structure
Signal lines of the write address channel
Signal lines of the write data channel
Signal lines of the write response channel
Signal lines of the read address channel
Signal lines of the read data channel
Transaction structure
- Number of transfers included in a burst
- AXI3 supports up to 16 transfers: Burst_Length = AxLEN[3:0] + 1
- AXI4 supports up to 256 transfers: Burst_Length = AxLEN[7:0] + 1
- AxSIZE: indicates how many bytes are transferred per transfer, up to 128 bytes
AxBURST: indicates the burst type
FIXED: fixed address mode, used for FIFO
INCR: incrementing address mode, used for RAM
Slave increments the address, supports 1 to 256 transfers, and supports unaligned transfers
WRAP: address increments and wraps around after reaching the upper limit, used for Cache
Access permissions
- ARPROT[2:0]: indicates the access permissions of a read transaction
- AWPROT[2:0]: indicates the access permissions of a write transaction
Cache support
- Various caches can be used during the transfer
- System-level caches at various levels, e.g., L2/L3 cache
- Cache inside the system bus (within the interconnect)
- AxCACHE[3:0]: indicates cache attributes
Response packet (response structure)
RRESP[1:0]，for read transfers
BRESP[1:0]，for write transfers
OKAY: indicates normal access success or exclusive access has failed
EXOKAY: indicates exclusive access success
SLVERR：slave error
DECERR: decode error
Write strobes
- WSTRB[n:0]: indicates whether the data on WDATA is valid, one bit represents one byte
- Mainly to support unaligned accesses
QoS signals
- The AXI bus provides additional signal lines to support quality of service
- AWQOS: 4-bit QoS, in the write address channel of each write transaction
- ARQOS: 4-bit QoS, in the read address channel of each read transaction
- 0 indicates the lowest priority, F indicates the highest priority
- Generally, system bus IP provides registers to configure the QoS of each master
Channel dependencies
- Dependency 1: WVALID is set valid before AWVALID is valid
- AWVALID indicates the write address channel is valid
- WVALID indicates the write data channel is valid
- Before the write address is valid, data can be sent out first
- Dependency 2: WLAST must be sent before BVALID is valid
- BVALID indicates the write response channel is valid
- WLAST indicates the last transfer in a transaction
- Before the write response packet is sent, all write data and addresses must be sent
- Dependency 3: RVALID cannot be valid before ARADDR is sent
- ARADDR indicates the address of the first transfer of a read transaction
- RVALID indicates the read data channel is valid
- If the address has not been fully transmitted, you should not see read data being returned.
lock access and exclusive access
Locked accesses
- Locked access is only in the AXI3 protocol; it has been deprecated in AXI4.
- AXI3 and AXI4 have the AxLOCK signal line.
- In AXI3, locked access is like locking the bus.
Exclusive access
Exclusive access is more efficient than locked access. It does not require locking the bus, and other masters can access the bus concurrently.
An exclusive monitor needs to be implemented on the slave side to coordinate exclusive access.
ARID Read transaction ID
AWID Write transaction ID
Access flow
- The master initiates an exclusive read. The slave’s exclusive monitor fills the ARID, address, and data into the table.
- The master initiates an exclusive write operation to the same address. The exclusive monitor checks the table and compares whether the AWID and ARID match.
- Response
- EXOKAY (success): if no other master has written to this address during this period, the exclusive write operation succeeds.
- OKAY (failure): if another master has written to this address during this period, the exclusive write fails.
Example: Exclusive access failure
Operation sequence:
- The master initiates the first exclusive read operation to address 0x8000.
- The master initiates the second exclusive read operation to address 0x8000.
- The master exclusively writes 0x3 to address 0x8000 -> success.
- The master exclusively writes 0x5 to address 0x8000 -> failure.
The first three operations:
There is a read transaction with the same ID during the exclusive write, so the write succeeds.
After the exclusive write succeeds, the exclusive monitor deletes all entries related to this address and ID from the table.
Exclusive Write fails because no read transaction with the same ID is found in the table.
Transaction ordering
AXI transaction ID
- AXI has a separate transaction ID for each transaction channel.
- All transfers must have an ID.
- Transfers in the same transaction have the same ID.
- Transaction IDs are used for out-of-order completion.
Write transaction ordering rules
- Write transaction ordering rule 1: The order of data writes in the write data channel must be consistent with the order of address transfers in the write address channel (data must follow the same order as address transfers).
In the write address channel, address A is sent first, then address B, so in the write data channel, data A is sent first, then data B.
- Write transaction rule 2: Write transactions with different IDs can complete in any order (data for different transaction IDs can be interleaved).
Transaction B completes before transaction A, even though transaction A was issued before transaction B.
- Write transaction rule 3: Write transactions with the same ID execute and complete in order (data with the same ID must follow in the order as issued).
Transaction B has a different ID from transactions A and C, so transaction B can complete in any order. Transactions A and C use the same ID, so transaction A must complete first, then transaction C.
Read transaction ordering rules
- Read transaction ordering rule 1: Transactions with different IDs in the read data channel can be in any order (data for different IDs has no ordering restrictions).
Although transaction B sends its address later than transaction A in the read address channel, transaction B can read data before transaction A.
- Read transaction rule 2: Transfers of transactions with different IDs can be interleaved on the read data channel (data with different transaction IDs can be interleaved)
Transaction A and transaction B read data in an interleaved manner.
- Read transaction rule 3: Read transactions with the same ID must complete in order (data with same ID must follow in the order as issued)
If transactions A and C have the same ID, and transaction A is issued before transaction C, then transaction A must complete before transaction C.
Unaligned address access
- The AXI bus supports unaligned address access using the byte strobes mechanism.
Starting from address 0x1, transfer 3 bytes first, and then the address is aligned.
AXI-Lite bus
Introduction to AXI4-Lite bus
- AXI4-Lite does not support burst mode, or burst length is 1.
- AXI4-Lite supports data widths of 32 bits or 64 bits.
- All AXI4-Lite accesses are Non-modifiable and Non-bufferable.
- Exclusive access is not supported.
Introduction to AXI5-Lite bus
- AXI5-Lite relaxes the data width and transaction transfer order requirements compared to AXI4-Lite.
- AXI5-Lite features
- Does not support burst mode, or burst length is 1.
- All accesses are Device and Non-bufferable.
- Exclusive access is not supported.
- When requests have different IDs, responses are allowed to be reordered.
New features added in AXI5/ACE5.
Summary
- The AXI bus defines 5 independent channels, each consisting of a set of signal lines
- The AXI bus defines the data structure and attributes of transfer transactions
- Burst length
- Transfer size
- Burst type
- Response packet
- Cache support
- Access permissions
- QoS signals
- Supports exclusive access
- Supports out-of-order transfers through transaction IDs
- Supports unaligned accesses