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2025-10-31
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This article introduces the basic concepts, features, and topology of the AXI bus in the ARM AMBA architecture. It discusses the five independent transmission channels of the AXI bus, the master-slave mechanism, the VALID/READY handshake process, and the read/write transaction flow. It also summarizes key features such as transaction structure, access permissions, cache support, and QoS, demonstrating its advantages of high performance and flexible scalability.
Reference Document:
Document: AMBA AXI and ACE Protocol Specification, Issue H, Part A & Part E
History of AMBA Bus Development
Applications of the AXI Bus
History of AMBA Bus Development
AXI Basic Concepts: Channels, Transfers, Transactions
What is a Bus
A bus consists of a single signal or a group of signals that transmit data or control information
On the bus, the sender encodes and transmits information according to the protocol-specified high and low level combinations, and the receiver then decodes it
External Bus and Internal Bus
- External buses connect peripheral devices, may be subject to external interference, connector and PCB losses, and poor signal integrity.
I2C，UART，SPI，PCIe，USB
- Internal buses are used within the SoC, routing inside the chip over very short distances, so many interference and signal integrity issues do not need to be considered.
AXI，UPI（intel）
Parallel bus and serial bus
- Parallel: Multiple data bits are transmitted simultaneously, requiring data alignment, which limits the frequency of parallel transmission and makes it prone to interference.
- Serial: Only one link is used, allowing high frequency to increase transmission speed.
Features of the AXI bus
- The AXI bus is a synchronous serial bus inside a chip.
- Advantages of the AXI bus
- High performance: high bandwidth, low latency, high frequency
- Flexible scalability of bus width and topology connections
- Compatible with AHB and APB buses
- Features of the AXI bus
- Separate address/control and data channels (separate read and write channels)
- Supports burst transmission
- Supports multiple outstanding addresses
- No strict timing between address and data phases
- Supports out-of-order transaction completion
- Supports unaligned data transfer
AXI topology
AXI uses master-slave mechanism
- Requests initiated by master
- Slave responds to requests
AXI channels
AXI defines 5 independent transfer channels to improve bandwidth
- Read address channel: AR
- Read data channel: R
- Write address channel: AW
- Write data channel: W
- Write response channel: B
Each channel consists of not just one signal line, but a group of signal lines
Write transfer transaction
- The address channel contains transfer control information
- Transfer transaction steps:
- The master initiates a write transfer through the write address channel, including address and control information
- The master writes data to the slave through the write data channel
- The slave responds through the write response channel
Read transfer transaction
- The master sends address and control information to the slave through the read address channel
- The slave returns data through the read data channel, with response information included in the returned data
Handshake process
- All 5 channels use the same handshake signals: VALID/READY handshake process
- The source generates a VALID signal to indicate that the address, data, control information, etc., are ready.
- The destination generates a READY signal to indicate that it is ready to accept information.
Handshaking occurs only when both READY and VALID signals are active simultaneously.
The difference between a transfer and a transaction.
Transfer
A single handshake process, transferring data once.
transaction
It involves multiple handshake signals, composed of multiple transfers.
Taking write as an example, address and control information are transmitted through the write address channel. Then data is transferred through the write data channel. Finally, a response is given through the write response channel.
There are a total of 3 transfers.
Example: Write transaction: single data item
Example: Read transaction: single data item
Example: Read transaction: multiple data items
Channel signals and transaction structure
Signal lines of the write address channel
Signal lines of the write data channel
Signal lines of the write response channel
Signal lines of the read address channel
Signal lines of the read data channel
Transaction structure
- How many transfers are included in one burst
- AXI3 supports up to 16 transfers: Burst_Length = AxLEN[3:0] + 1
- AXI4 supports up to 256 transfers: Burst_Length = AxLEN[7:0] + 1
- AxSIZE: Indicates how many bytes are transferred in one transfer, up to 128 bytes
AxBURST: Indicates the burst type
FIXED: Fixed address mode, used for FIFO
INCR: Incrementing address mode, used for RAM
slave increments address, supports 1 to 256 transfers, supports unaligned transfers
- WRAP: Address increments and wraps around after reaching the upper limit, used for Cache
Access permissions
- ARPROT[2:0]: Indicates access permissions for read transactions
- AWPROT[2:0]: Indicates access permissions for write transactions
Cache support
- Various caches can be utilized during transfers
- System-level caches at various levels, e.g., L2/L3 cache
- Cache within the system bus (with the interconnect)
- AxCACHE[3:0]: Indicates cache attributes
Response structure
RRESP[1:0]，for read transfers
BRESP[1:0]，for write transfers
OKAY: Indicates normal access succeeded or exclusive access has failed
EXOKAY: Indicates exclusive access success
SLVERR：slave error
DECERR: Decode error
Write strobes
- WSTRB[n:0]: Indicates whether data on WDATA is valid, one bit per byte
- Primarily to support unaligned accesses
QoS signals
- The AXI bus provides additional signal lines to support quality of service
- AWQOS: 4-bit QoS, in the write address channel of each write transaction
- AWQOS: 4-bit QoS, in the read address channel of each read transaction
- 0 indicates lowest priority, F indicates highest priority
- Typically, system bus IP provides registers to configure the QoS of each master
Channel dependencies
- Dependency 1: WVALID is set valid before AWVALID becomes valid
- AWVALID indicates the write address channel is valid
- WVALID indicates the write data channel is valid
- Data can be sent out before the write address is valid.
- Dependency 2: WLAST must be sent before BVALID is valid.
- BVALID indicates the write response channel is valid.
- WLAST indicates the last transfer in a transaction.
- All write data and addresses must be sent before the write response packet is sent.
- Dependency 3: RVALID cannot be valid before ARADDR is sent.
- ARADDR indicates the address of the first transfer in a read transaction.
- RVALID indicates the read data channel is valid.
- If the address has not been sent, no read data should be seen returned.
lock access and exclusive access
Locked accesses
- Locked access is only in the AXI3 protocol; it is deprecated in AXI4.
- There is an AxLOCK signal line in both AXI3 and AXI4.
- In AXI3, locked access is similar to locking the bus.
Exclusive access
Exclusive access is more efficient than locked access; it does not require locking the bus, and other masters can access the bus simultaneously.
An exclusive monitor needs to be implemented on the slave side to coordinate exclusive access.
ARIDID of the read transaction.
AWIDWrite transaction ID
Access flow
- The master initiates an exclusive read. The slave’s exclusive monitor fills the ARID, address, and data into the table.
- The master initiates an exclusive write operation to the same address. The exclusive monitor checks the table and compares whether the AWID and ARID match.
- Response
- EXOKAY (success), if no other master writes to this address during this period, the exclusive write operation succeeds.
- OKAY (failure), if another master writes to this address during this period, the exclusive write fails.
Example: Exclusive access failure
Operation sequence:
- The master initiates the first exclusive read operation to address 0x8000.
- The master initiates the second exclusive read operation to address 0x8000.
- The master exclusively writes 0x3 to address 0x8000 -> success
- The master exclusively writes 0x5 to address 0x8000 -> failure
First three steps:
During exclusive write, there is a read transaction with the same ID, so the write succeeds
After the exclusive write succeeds, the exclusive monitor removes all entries related to this address and ID from this table
During exclusive write, no read transaction with the same ID is found in the table, so it fails
Transaction ordering
AXI transaction ID
- AXI has a unique transaction ID for each transaction channel
- All transfers must have an ID
- Transfers within the same transaction have the same ID
- Transaction IDs are for out-of-order processing
Write transaction ordering rules
- Write transaction ordering rule 1: The order of data writes on the write data channel must match the order of address transfers on the write address channel (data must follow the same order as address transfers)
On the write address channel, address A is sent first, then address B, so on the write data channel, data A is sent first, then data B
- Write Transaction Rule 2: Write transactions with different IDs can complete in any order (data for different transaction IDs can be interleaved)
Transaction B completes before transaction A, even though transaction A was issued before transaction B
- Write Transaction Rule 3: Write transactions with the same ID must be executed and completed in order (data with the same ID must follow in the order as issued)
Transaction B has a different ID from transactions A and C, so transaction B can complete in any order. Transactions A and C use the same ID, so transaction A must complete first, followed by transaction C
Read Transaction Ordering Rules
- Read Transaction Ordering Rule 1: Transactions with different IDs on the read data channel can be in any order (data for different IDs has no ordering restrictions)
Although transaction B sends its address later than transaction A on the read address channel, transaction B can read data before transaction A
- Read Transaction Rule 2: Transfers of transactions with different IDs on the read data channel can be interleaved (data with different transaction IDs can be interleaved)
Transaction A and Transaction B interleaved reading data
- Read transaction rule 3: Read transactions with the same ID must complete in order (data with same ID must follow in the order as issued)
Transactions A and C have the same ID; transaction A is issued before transaction C, so transaction A must also complete before transaction C
Non-aligned address access
- The AXI bus supports non-aligned address access using the byte strobes mechanism
Starting from address 0x1, first transfer 3 bytes, then the address becomes aligned
AXI-Lite bus
Introduction to AXI4-Lite bus
- AXI4-Lite does not support burst mode, or the burst length is 1
- AXI4-Lite supports data widths of 32 bits or 64 bits
- All accesses on AXI4-Lite are Non-modifiable and Non-bufferable
- Does not support exclusive access
Introduction to AXI5-Lite Bus
- AXI5-Lite relaxes the requirements for data width and transaction ordering compared to AXI4-Lite
- Features of AXI5-Lite
- Does not support burst mode, or burst length is 1
- All accesses are Device and Non-bufferable
- Does not support exclusive access
- Allows reordering of responses when requests have different IDs
New features in AXI5/ACE5
Summary
- The AXI bus defines 5 independent channels, each consisting of a set of signal lines
- The AXI bus defines the data structure and attributes of transfer transactions
- Number of bursts
- Size of transfer
- Burst type
- Response packet
- Cache support
- Access brand new
- QoS signal
- Support exclusive access
- Support out-of-order transmission via transaction ID
- Support unaligned access